1. Field of Invention
The present invention relates to a graphics display system that reads pixel data periodically from a frame buffer memory for screen display. More specifically, the invention relates to a method and structure for reducing the amount of pixel data transmitted from the frame buffer memory during refresh operations.
2. Description of Related Art
FIG. 1 is a block diagram of a typical graphics system 100 of a personal computer. System 100 is a multi-processor system which includes display controller 101, graphics processor 102, system processor 103, video processor 104, memory interface 105, frame buffer memory 106, system bus 107, CRT display 108 and system processor interface 109. Processors 101-104 are each coupled to system bus 107, with system processor 103 being coupled to bus 107 through system processor interface circuit 109. Frame buffer memory 106 is coupled to system bus 107 through memory interface 105. Frame buffer memory 106 is typically constructed using dynamic random access memory (DRAM) and has the capacity to store pixel data for at least one frame of a video display image. Processors 101-104 each access frame buffer memory 106 via bus 107. Processors 101, 102 and 104, system processor interface 109, and memory interface 105 are usually integrated into a single chip.
In general, the performance of system 100 is limited by the bandwidth of frame buffer memory 106. More specifically, display controller 101 consumes most of the data bandwidth of frame buffer memory 106 when CRT display 108 is in higher resolution modes with more bits per pixel (for more color variations). For example, if CRT display 108 is to display an image having 1,024.times.768 pixels at 24 bits (three 8-bit bytes) per pixel, frame buffer memory 106 must have a capacity of 2.36 MBytes to store the entire image. To minimize flicker of the image on display 108, a relatively high screen refresh rate, such as 75 Hz to 100 Hz, should be used. In such a system, the average data bandwidth requirement is approximately 177 to 236 MBytes per second (i.e., 2.36 MBytes are read from frame buffer memory 106 and displayed 75 to 100 times each second). Subtracting horizontal and vertical retrace time, the actual peak data bandwidth requirement of frame buffer memory 106 is approximately 250 to 390 MBytes per second. At higher resolutions, such as 1,280.times.1,024 pixels at 24 bits per pixel, the actual data bandwidth requirement of frame buffer memory 106 is 400 to 600 MBytes per second. The above-listed actual data bandwidth requirements only include the bandwidth required for refreshing the CRT display 108.
Pixels used to form graphics and video images generally have many repetitions in both time and space. That is, pixels in close physical proximity with one another often have the same value, and consecutive pixels will often have the same value over a relatively long interval of time (as compared to the screen refresh rate). Compression algorithms such as JPEG and MPEG have been developed to take advantage of these temporal and spatial redundancies. Such compression algorithms can provide compression ratios from 5:1 to 100:1, thereby reducing the amount of data required to represent the image. These algorithms, however, are very complex and require significant processing power to encode and decode. Therefore, encoding (compression) is usually done once with the resultant data primarily for storage and distribution, and decoding (de-compression) is done only once for the playback operation.
Modification or manipulation of pixel data in real time is difficult unless the pixel data is present in a de-compressed format in frame buffer memory 106. Moreover, in computer graphics display system 100, many applications may need to access or modify the contents of frame buffer memory 106. For these reasons, the pixel data is generally maintained in a de-compressed format in frame buffer memory 106. Because pixel data is accessed in a de-compressed format when refreshing CRT display 108, general compression/de-compression algorithms are not suitable for reducing the data bandwidth requirement of frame buffer memory 108 during the refreshing of CRT display 108.
It would therefore be desirable to have a structure and method to reduce the data bandwidth requirement of a frame buffer memory during a display refresh operation. It would also be desirable for such a structure and method to have minimum circuit and data access overhead. Such a structure and method would advantageously free up frame buffer memory bandwidth to enable other system processors and processes to achieve higher performance.